Performance Interfaces

Performance interfaces are to performance what semantic interfaces (documentation, header files, specifications, etc.) are to functionality: succinct descriptions of the performance one can expect when running that code. Performance interfaces differ from performance specifications and/or models in that they are succinct and highly accessible to the average developer, in the same way that a semantic interface differs from a formal specification.

Our research pursues three broad directions:

• Extracting performance interfaces from system implementations, and using them to develop applications that meet their performance expectations
• Designing systems that exhibit predictable performance and are thus amenable to being described using a performance interface
• Formally verifying that systems code will indeed perform as advertised by its performance interface

Publications

• Automatically Reasoning About How Systems Code Uses the CPU Cache
  Rishabh Iyer, Katerina Argyraki, George Candea.
  OSDI 2024.
  Also accepted to the Linux Plumbers Conference 2024.
  [slides] [talk video]

• Performance Interfaces for Hardware Accelerators
  Jiacheng Ma, Rishabh Iyer, Sahand Kashani, Mahyar Emami, Thomas Bourgeat, George Candea.
  OSDI 2024.
  [slides] [code] [talk video]

• Achieving Microsecond-Scale Tail Latency Efficiently with Approximate Optimal Scheduling
  Rishabh Iyer, Musa Unal, Marios Kogias, George Candea.
  SOSP 2023.
  [slides] [code] [talk video]

• Latency Interfaces for Systems Code
  Rishabh Iyer.
  PhD Thesis at EPFL, 2023.

• The Case for Performance Interfaces for Hardware Accelerators
  Rishabh Iyer, Jiacheng Ma, Katerina Argyraki, George Candea, Sylvia Ratnasamy.
  HotOS 2023.
  [slides]

• Performance Interfaces for Network Functions
  Rishabh Iyer, Katerina Argyraki, George Candea.
  NSDI 2022.
  [slides] [talk video] [code]

• Performance Contracts for Software Network Functions
  Rishabh Iyer, Luis Pedrosa, Arseniy Zaostrovnykh, Solal Pirelli, Katerina Argyraki, George Candea.
  NSDI 2019.
  [slides] [talk video] [code] [website]

Software

• LPN is a toolchain that let hardware developers to specify a performance-only model of their hardware accelerators with a representation called Latency Petri Net (LPN). The toolchain includes different tools that transform the LPN into different representations for different usages (performance interfaces, verification conditions, fast simulators and formats for visualization).
• PIX is a toolchain that automatically extracts performance interfaces from software network function (NF) implementations. The resulting performance interfaces are accurate yet orders of magnitude simpler than the code itself, and they take mere minutes to extract.
• Concord is a runtime that demonstrates how to achieve predictable, microsecond-scale control of execution time with low throughput overhead.
• Bolt is a precursor to PIX, and it is used to automatically generate performance contracts for software network functions.

This is a joint project with the Dependable Systems Lab at EPFL.